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ILX506
5000-pixel CCD Linear Image Sensor (B/W) For the availability of this product, please contact the sales office.
Description The ILX506 is a reduction type CCD linear sensor developed for high resolution facsimiles and copiers. This sensor reads A3-size documents at a density of 400 DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use. In addition, reset pulse can be switched between internal generation and external input. Features * Number of effective pixels: 5000 pixels * Pixel size: 7m x 7m (7m pitch) * Built-in timing generator and clock-drivers * Ultra low lag/ultra high sensitivity/low dark output * Single output method * Maximum clock frequency: 12.5MHz Absolute Maximum Ratings * Supply voltage VDD1 VDD2 * Operating temperature * Storage temperature Pin Configuration (Top View) 22 pin DIP (Ceramic)
11 6 -10 to +60 -30 to +80
V V C C
VGG GND VDD1 VOUT GND ROG VDD2 VDD2 RSSW
1 2 3 4 5 6 7 8 9
1
22 CLK 21 20 19 18 17 16 15 14 13 VDD1 RS/SH VDD1 VDD1 GND VDD2 GND T4 T3 T2
T1 10 GND 11 5000
12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E92239B78-PS
Block Diagram
VDD1
T3
GND
VDD1
VDD1
VDD2
21 18 17 16 15 14 12
19 13
Clock-drivers
CCD analog shift register . Read out gate
S2
D28
D29
D30
D18
D17
* Output amplifier * Sample-and-hold circuit * Feed through suppression circuit
Read out gate CCD analog shift register
VGG Clock-drivers
1
Clock pulse generator Sample-and-hold pulse generator
Mode selector
S4999
S5000
D31
D32
D33
Read out gate pulse generator
D34
10 11 6
4
S1
VOUT
GND
2 7 22
3
5 8
T4
9
20
VDD1
GND
GND
VDD2
VDD2
T1
T2
CLK
GND
RSSW
RS/SH
ROG
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ILX506
ILX506
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol VGG GND VDD1 VOUT GND ROG VDD2 VDD2 Description Output circuit gate bias GND 9V power supply Signal output GND Clock pulse 5V power supply
5V power supply 1 Reset pulse switchover pin RSSW T1 GND T2 T3 T4 GND VDD2 GND VDD1 VDD1 Test pin (5V) GND Test pin (GND) Test pin (5V) Test pin (GND) GND 5V power supply GND 9V power supply 9V power supply
RS/SH1 Clock pulse or with S/H; without S/H switch VDD1 CLK 9V power supply Clock pulse
1 Output mode is changeable as follows. 20pin 9pin GND VDD1 GND Internal RS without S/H -- VDD1 Internal RS with S/H -- RS -- External RS without S/H
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ILX506
Recommended Voltage Item VDD1 VDD2 Min. 8.5 4.75 Typ. 9.0 5.0 Max. 9.5 5.25 Unit V V
Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
Clock Characteristics Item Input capacity of CLK pin Input capacity of ROG pin Input capacity of RS/SH pin Frequency of CLK Frequency of RS Symbol CCLK CROG CRS/SH fCLK fRS Min. -- -- -- -- -- Typ. 10 10 10 1 1 Max. -- -- -- 12.5 12.5 Unit pF pF pF MHz MHz
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ILX506
Electro-optical Characteristics (Note 1) (Ta = 25C, VDD1 = 9V, VDD2 = 5V, CLK = 1MHz, Internal RS mode without S/H, Light source = 3200K, IR cut filter, CM-500S (t = 1.0mm)) Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Even and odd black level DC difference Dark voltage average Dark signal nonuniformity Image lag 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level Dynamic range Symbol R1 R2 PRNU VSAT SE V VDRK DSNU IL IVDD1 IVDD2 TTE ZO VOS DR Min. 7.5 -- -- 1.0 0.072 -- -- -- -- -- -- 92 -- -- 500 Typ. 10.8 24.6 4 1.5 0.139 1.0 0.3 0.6 0.02 16 3 98 600 3.0 5000 Max. 13.9 -- 10 -- -- 10.0 2 3 -- 32 7 -- -- -- -- Unit V/(lx * s) V/(lx * s) % V lx * s mV mV mV % mA mA % V -- Remarks Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9 Note 10 -- -- -- -- Note 11 Note 12
Notes) 1) In accordance with the given electrooptical characteristics, the even black level is defined as the mean value of D8, D10, D12 to D14. The odd black level is defined as the mean value of D7 , D9, D11 and D13. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) W lamp (2854K) 4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. PRNU = (VMAX - VMIN)/2 x 100 [%] VAVE
Where the 5000 pixels are divided into blocks of 100, even and odd pixels, respectively. The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 5) Use below the minimum value of the saturation output voltage. 6) Saturation exposure is defined as follows. SE = VSAT R1
7) Indicates the DC difference in value between odd black level and even black level. 8) Optical signal accumulated time int stands at 10ms.
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ILX506
9) The difference between the maximum and mean values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time int stands at 10ms. 10) VOUT = 500mV (Typ.) 11) Vos is defined as indicated below.
Vout VOS GND
12) Dynamic range is defined as follows. DR = VSAT VDRK
When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time.
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Application Circuit
CLK
RS
9V
5V
22 CLK VDD1 (D) RS/SH (D) VDD1 (A) VDD1 (A) GND (D) VDD2 (D) GND (D) T4 (D) T3 (D) T2 (D)
21
20
19
18
17
16
15
14
13
12
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(A) VGG 1 (A) GND 5 ROG 6 (D) VDD2 7 (A) GND 2 (A) VDD1 3 (A) VOUT 4 (D) VDD2 8 10/16V 1k Output signal 2SA1175 ROG
(D) RSSW 9
(D) T1 10
(A) GND 11
0.01
0.01
10/10V 0.01
10/16V
This application circuit shows when RS is used externally. connect pins (A) to the analog ( When noise influencetointo output signal is large,and also use aindicated by capacitor of large power supply and ) pins indicated by (D) the digital power supply, decoupling capacitance. ILX506 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Clock Timing Diagram
5
ROG
0
5034
1
1
5
CLK
0
5
RS
D1
D2 D3 D4 D5 D6
D14 D15 D16 D17 D18
D26 D27 D28 S1 S2 S3 S4
VOUT
Optical black (28 pixels)
Dummy signal (28 pixels)
Effective picture elements signal (5000 pixels)
1-line output period (5034 pixels) This clock timing diagram shows when RS is used externally. ILX506
S4997 S4998 S4999 S5000 D29 D30 D31 D32 D33 D34
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0
2 3 4
Dummy signal (6 pixels)
2
ILX506
Clock Pulse Waveform Conditions CLK, ROG pulse related
t8 t9
ROG
t2
CLK
t1
t3
Internal RS mode
t8 t9
CLK
t4
t5
Vout t10 t11 t10
External RS mode
CLK
t4
t5
t9
t8
RS
t7
t6
t13 t12
t10
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ILX506
Item ROG, CLK pulse timing ROG, CLK pulse timing ROG pulse high level period CLK pulse high level period CLK pulse low level period RS pulse low level period CLK, RS pulse timing Input clock pulse rise/fall time Input clock pulse voltage High level Low level Internal RS Signal output delay time External RS 1 Recommended condition during CLK = 1MHz. t1 t3 t2 t4 t5 t6 t7 t8, t9
Symbol
Min. 100 800 800 40 40 25 60 -- 4.5 0 -- -- -- --
Typ. 200 1000 1000 5001 5001
Max. -- -- -- -- --
Unit ns ns ns ns ns
ns 1001 -- 1 10 + t4 + t5 ns 550 5 5.0 -- 95 70 45 60 10 5.5 0.5 -- -- -- -- ns V V ns ns ns ns
VCLK, VROG VRS t10 t11 t12 t13
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ILX506
Example of Representative Characteristics (VDD1 = 9V, VDD2 = 5V, Ta = 25C)
Spectral sensitivity characteristics (Standard characteristics)
1.0
0.8
Relative sensitivity
0.6
0.4
0.2
0 400
500
600
700 800 Wavelength [nm]
900
1000
MTF of main scanning direction (Standard characteristics)
0 1.0 Spatial frequency [cycles/mm] 14.3 28.6 42.9 57.1 71.4
0.8
0.6
MTF
0.4 0.2 0 0 0.2 0.4 0.6 0.8 Normalized spatial frequency 1.0
Dark signal output temperature characteristics (Standard characteristics)
Integration time output voltage characteristics (Standard characteristics)
10 5
Output voltage rate
Output voltage rate
0
1
1 0.5
0.5
0.1 10 20 30 40 50 Ta - Ambient temperature [C] 60
0.1 1 5 int - Integration time [ms] 10
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ILX506
Operational frequency characteristics of the VDD1 supply current (Standard characteristics)
Operational frequency characteristics of the VDD2 supply current (Standard characteristics)
IVDD1 - VDD1 supply current [mA]
IVDD2 - VDD2 supply current [mA]
0
40
15
30
10
20
5
10
0 2 4 6 8 10 fCLK - CLK clock frequency [MHz] 12.5
0 0 2 4 6 8 10 fCLK - CLK clock frequency [MHz] 12.5
Offset level vs. VDD1 characteristics (Standard characteristics)
6 Ta = 25C 5 5 6
Offset level vs. VDD2 characteristics (Standard characteristics)
Ta = 25C
Vos - Offset level [V]
4
Vos - Offset level [V]
4
3
3
2
Vos VDD1
2
0.35 1
Vos VDD2
-0.14
1
0 8.5 VDD1 [V] 9 9.5
0 4.75 VDD2 [V] 5 5.25
Offset level vs. Temperature characteristics (Standard characteristics)
6
5
Vos - Offset level [V]
4
3
2
Vos Ta
-0.8mV/C
1
0 0 10 30 50 20 40 Ta - Ambient temperature [C] 60
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ILX506
Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Regulation for raising and lowering the power supply voltage When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V). 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficienty. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
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Package Outline
Unit: mm
22pin DIP (400mil)
22 12
8.1
0 to 9 10.0 0.5 10.16
8.2 0.8
49.0 0.5 35.0 (7m x 5000Pixels)
V No.1 pixel 11
5.0 0.5
1
0.97
1st. pin index 1. The height from the bottom to the sensor surface is 1.42 0.3mm. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.
4.0 0.5
2.3
2.54 0.3
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
Ceramic
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
3.9g
3.1 0.5
0.51
0.25
(AT STAND OFF)
H
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ILX506

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